/*
*	This is the regisiter between Fetch and Decode
*	Done in 2011.4.5
*
*/

module Reg_FD(
	instrIn,
	instrOut,
	PCPlus4In,
	PCPlus4Out,
	CLR,
	CLK,
	EN
);
	input[31:0] instrIn,PCPlus4In;
	input CLR,EN,CLK;
	output[31:0] instrOut,PCPlus4Out;
	reg[31:0] instrOut,PCPlus4Out;
	integer ClockCount;
	//initial PC
	initial begin
		instrOut = 0;
		PCPlus4Out = 4;
		ClockCount = 0;
	end
	
	//when CLR come through a posedge begin work
	
	always @(posedge CLK) begin
		if(ClockCount == 0) begin
			if(EN) begin
				if(CLR) begin
					instrOut	<=	0;
					PCPlus4Out	<=	0;
				end
				else begin
					instrOut	<=	instrIn;
					PCPlus4Out	<=	PCPlus4In;	
				end
			end
		end
		ClockCount =(ClockCount + 1) % 2;
	end

endmodule
